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INTEGRATED CIRCUITS
SA2400A Single chip transceiver for 2.45 GHz ISM band
Product data 2002 Nov 04
Philips Semiconductors
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
1. DESCRIPTION
The SA2400A is a fully integrated single IC RF transceiver designed for 2.45 GHz wireless LAN (WLAN) applications. It is a direct conversion radio architecture that is fabricated on an advanced 30 GHz fT BiCMOS process. The SA2400A combines a receiver, transmitter, and LO generation into a single IC. The receiver consists of a low-noise amplifier, down-conversion mixers, fully integrated channel filters, and an Automatic Gain Control (AGC) with an on-chip closed loop. The transmitter contains power ramping, filters, up-conversion, and pre-drivers. The LO generation is formed by an entirely on-chip VCO and a fractional-N synthesizer. Typical system performance parameters for the receiver are 93 dB gain, 7.5 dB noise figure, input-referred third-order intercept point (IIP3) of +1 dBm, AGC settling time of 8 s, and Tx-to-Rx switching time of 3 s. The transmitter typical system performance parameters are an output power range from -7 dBm to +8 dBm in 1 dB steps, -40 dBc carrier leakage after calibration, 22 dB sideband suppression, in-band common mode rejection of 30 dB, and Rx-to-Tx switching time of 3 s.
* An I/Q upconverter from baseband directly to 2.45 GHz, with
+8 dBm output power, -40 dBc typical carrier leakage (calibrated) and 3 s (typical) Rx to Tx switching time, and comprising the following: - Wide band IQ modulator producing better than 14% EVM for 11 Msymbols/s QPSK modulation - Integrated reconstruction and spectral shaping filters at I and Q modulation input that is driven by an external D/A. High common mode rejection to input ground bounce. - FIR-DACs for digital I/Q input feeding the analog signal path and including additional filtering for spectral shaping. - 2.45 GHz power amplifier driver with +8 dBm maximum output, 15 dB adjustable gain in 1 dB steps and a second switched output at -1.5 dBm power level with similar gain adjustments that are set by a separate register. - Completely on-chip calibration for Carrier Leakage compensation. - Internal power ramping with 2 s delay and 0.5 s ramp-up time.
2. FUNCTIONAL BLOCKS AND FEATURES
The block diagram of the SA2400A Direct Conversion transceiver is given in Figure 1. It consists of the following functional blocks:
* A 79 dB adjustable gain range direct conversion zero IF receiver
with 3 s (typical) Tx to Rx switching time, and comprising the following: - Front-end LNA with two internal gain states - A fast on-chip closed loop composite RF and IF AGC with zoomed analog RSSI output and 8 s settling time - Quadrature downconverters from 2.45 GHz RF directly to zero IF
* A fractional-N frequency synthesizer with on-chip VCO and XO * A 3-wire bus for control of most blocks * An additional high speed 3-wire bus for full control of Rx-Gain and
DC-offset compensation parameters with 44Mbits/s.
* Fast Tx-Rx switching based on a single digital input pin. * Reference currents and voltage for supply of Baseband Processor
and PA-chip.
3. APPLICATIONS
- On-chip fast baseband DC cancellation with automatically stepped bandwidths of 10 MHz, 1 MHz, 100 kHz, and 10 kHz, settling within 8-13 s for a DC error of 10% that decays to 1%. - Fully integrated channel filters, appropriate for 11 Msymbols/s QPSK modulation RF bandwidth.
* IEEE 802.11 and 802.11b radios
- Supports DSSS and CCK modulation - Supports data rates: 1, 2, 5.5, and 11 Mbps
* 2.45 GHz ISM band wireless communication devices
Table 1. Ordering Information
PACKAGE TYPE NUMBER SA2400ABE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm VERSION SOT313-2
2002 Nov 04
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853-2320 28727
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
4. BLOCK DIAGRAM
2 2 RF_IN
RX_OUT_I RSSI A/D
RSSI 2
RX_OUT_Q
AGC STATE MACHINE SEN SCLK SDATA 0 90 CONTROL :2 FILTER TUNING 0 90 XO 2 TX_OUT_HI FIRDAC FIRDAC 2 TX_OUT_LO
AGCRESET AGCSET
V_TUNE CP LOCK XTAL 2 REF_CLK TX_IN_I DATA_I DATA_Q TX_IN_Q
TXRX TX_HI
PLL 2
D/A POWER DETECTOR TXCAL STATE MACHINE A/D D/A
SR02386
Figure 1. SA2400A functional block diagram.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
5. PINNING INFORMATION
TX_OUT_HI_M TX_OUT_HI_P TX_OUT_LO
A_GND
A_GND
A_GND
SDATA
A_V DD
48
47
46
45
44
43
42
41
40
39
38
37
TX/RX
TX_HI
SCLK
SEN
AGCRESET
1
36
TX_IN_I_P/ TX_DATA_I TX_IN_I_M/ TX_DATA_Q TX_IN_Q_P
AGCSET
2
35
IDCOUT
3
34
A_GND GND_LNA
4 5
33 32
TX_IN_Q_M A_V DD
RF_IN_P
6
SA2400A
31
RX_OUT_Q_P
RF_IN_N
7
30
RX_OUT_Q_M
GND_LNA
8
29
RX_OUT_I_P
A_V DD
9 10
28
RX_OUT_I_M D_GND
TEST1
27
TEST2
11
26
REF_CLK_OUT
V_2P5
12
25
PLL_GND
13
14
15
16
17
18
19
20
21
22
23
D_VDD
VCO_M
LOCK
XTAL_1
VCO_GND
V_TUNE
VCO_VDD
VDD _PLL
XTAL_2
RSSI
VCO_P
CP
24
SR02387
Figure 2. Pin configuration.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 2. Pin description
PIN type is designated by A = Analog, D = Digital, I = Input, O = Output SYMBOL AGCRESET AGCSET IDCOUT A_GND GND_LNA RF_IN_P RF_IN_N GND_LNA A_VDD TEST_1 TEST_2 V_2P5 RSSI D_VDD V_TUNE VCO_GND VCO_VDD VCO_P VCO_M VDD_PLL CP LOCK XTAL_1 XTAL_2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION AGC start input AGC settled output Tx-mode: DC reference current Analog Ground Analog Ground RF input (positive) RF input (negative) Analog Ground Analog Supply Test pin Test pin DC reference voltage RSSI output signal Digital Supply VCO tuning voltage VCO ground VCO Supply VCO output/ External VCO input VCO output/ External VCO input Synthesizer Supply Charge pump output Synthesizer lock indicator Crystal input Crystal input AO AO AI AI AI/O AI/O AI AO AO AI AI TYPE DI DO AO SYMBOL PLL_GND REF_CLK_OUT D_GND RX_OUT_I_M RX_OUT_I_P RX_OUT_Q_M RX_OUT_Q_P A_VDD TX_IN_Q_M TX_IN_Q_P TX_IN_I_M/ TX_DATA_Q TX_IN_I_P/ TX_DATA_I TX/RX SCLK SDATA SEN A_GND TX_OUT_HI_M TX_OUT_HI_P A_GND TX_OUT_LO A_VDD TX_HI A_GND PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DESCRIPTION Synthesizer Ground Reference clock output Digital and Analog Ground Receive output Receive output Receive output Receive output Analog Supply Transmit input Transmit input Transmit input Transmit input Tx/Rx mode select Three-wire bus clock Three wire bus data Three wire bus enable Analog Ground Transmit output, high power Transmit output, high power Analog Ground Transmit output, low power Analog Supply Transmit output power level select Analog Ground DI AO AO AO AI AI AI/DI AI/DI DI DI DI/O DI AO AO AO AO AO TYPE
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
6. FUNCTIONAL DESCRIPTION
The SA2400A transceiver is intended for operation in the 2.45 GHz band, specifically for IEEE 802.11b 1 and 2 Mbits/s DSSS, and 5.5 and 11 Mbits/s CCK standards. Throughout this document, the operating RF frequency refers to the ISM band between 2.4 GHz and 2.5 GHz.
high-pass will then remain set to the 10 kHz cutoff frequency until a new AGC cycle is started. Whenever there is a frequency change in the high-pass filter lower cutoff, the DC offset can change from a very low value to about 50% (1 MHz 100 kHz step) or 10% (100 kHz 10 kHz step) of the signal level. This DC offset then decays according to the high-pass response of the filter. The cutoff frequency of the high-pass filter can also be selected manually by using the RXMGC mode.
6.1 RF VCO
The local oscillator is common to both the transmitter and the receiver. The RF VCO is a differential 4.8 GHz oscillator with the frequency determining components internal to the IC. The VCO is connected internally to a frequency divider and a quadrature generator circuit which produces the LO for the IQ up- and downmixer. The divider output is also internally connected to the synthesizer, which can be programmed in order to produce steps of 0.5 MHz for the desired LO frequency. At the time of power-up, the VCO must be calibrated by invoking the VCOCALIB mode by means of the three-wire bus. This operation will select an appropriate frequency band in the VCO, thus compensating for process tolerances. The calibration takes up to 2.2 ms, after which the IC automatically enters the SLEEP mode. The synthesizer registers 0x00 through 0x03 must be re-programmed after completing the VCOCALIB. The 2.45 GHz LO can also be injected externally.
6.6 AGC
The receiver contains a fully integrated Automatic Gain Control loop. It works by adjusting the internal gain such that the Rx output amplitude, as measured by the RSSI (see below), meets a predefined target value. By default, the AGC is always set to a default maximum gain (adjustable by register value GMAX) whenever the SA2400A enters the RECEIVE mode of operation from another operational mode. It takes 5 s for the receiver to settle when it enters this mode, which includes the time for DC offsets to be removed with a 1 MHz lower cut-off frequency of the high-pass filtering. This lower cut-off frequency of 1 MHz remains unchanged as long as the AGC remains in the default maximum gain state. The AGC must be invoked by providing a 0-to-1 transition on the AGCRESET pin, and keeping the signal on that pin to 1 for at least 5 s. By successively reducing the gain from its initial maximum value, the loop searches for the correct gain value to provide a nominal output amplitude of 500 mVpeak, differential for a QPSK signal (within 3 dB dynamic error) at the output pins. This is achieved after a maximum of 8 s. This time is defined by wait periods necessary to settle the receiver after gain switching actions. The individual wait periods can be adjusted by means of register settings. After completing the AGC settling process, the AGCSET pin is set to 1 by the algorithm. The receiver gain then will not change again until another pulse is issued on the AGCRESET pin. For a subsequent AGC operation, the receiver needs to enter its maximum gain state again. If another AGCRESET signal (as described above) is issued, the settling period will take an extra 3 s, up to a total of 11 s, since the first 3 s will be spent on entering maximum gain mode and settling the receiver thereafter. To shorten this operation, the receiver can be forced to maximum gain (e.g., at a time when no signal is present) by issuing a 0-1-0 pulse of maximum 1 s pulse width on the AGCRESET pin. The receiver will then enter maximum gain mode (the AGCSET signal will not be set to 1 after this), and a following 0-to-1 transition on the AGCRESET pin will start the settling sequence from maximum gain, which will then take a maximum of 8 s. The receiver gain can also be selected manually by using the RXMGC mode. The settling target can be adjusted by 7 dB from the nominal level of 500 mVpeak, differential by means of register settings. Note: When doing measurements with a single-tone RF signal, the amplitude at the Rx outputs after settling the AGC will be lower, at about 300 mVpeak, differential.
6.2 RF Low Noise Amplifier
The RF LNA has differential inputs and an external balun is needed in the case of single-ended operation. It has two gain states which are controlled internally by the on-chip automatic gain control, or manually via the 3-wire bus.
6.3 Downconversion mixers
The RF signal is converted down directly to baseband by quadrature image-reject mixers.
6.4 Receiver low-pass filter, baseband amplifiers
The I and Q low-pass filters are fully integrated Chebychev active filters. The I and Q pass band extends from DC to a -3 dB corner at 7 MHz. Additional adjustable gain is provided in baseband amplifiers to achieve a total adjustable gain range of 79 dB. The Rx output is provided in the form of differential I and Q signals, which must be DC coupled to the ADC inputs on a base band IC.
6.5 DC cancellation
The Rx chain also integrates a high-pass filter (DC notch) for cancellation of the DC offset inherent to zero-IF operation. The high-pass filter has a programmable lower 3 dB cutoff frequency of 10 MHz, 1 MHz, 100 kHz or 10 kHz. The DC offset cancellation occurs simultaneously with the AGC settling process. During the AGC settling phase (see below) the cutoff frequency is dynamically selected between 10 MHz and 1 MHz to quickly reduce DC offset values from +50 dBc to below -20 dBc relative to a -76 dBm antenna input signal before the RSSI (see below) is internally sampled. After the AGC settling, the high pass is configured for 100 kHz for 5 s before switching to a final 10 kHz cutoff frequency. The low value of 10 kHz is required for minimizing the signal distortion created by a high-pass function at zero frequency. The
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
6.7 AGC Handshake
On the digital input pin AGCRESET, a 0-to-1 transition clears AGCSET output to logic 0 and starts the AGC cycle. At the end of the AGC settling, the AGCSET output is asserted to logic 1. The AGCRESET input can then be reset to logic 0. At any time in the RECEIVE mode the AGC can be forced to the maximum gain by giving the AGCRESET signal as described, but by additionally re-setting it to logic 0 within 1 s. The AGCSET indication is not given in this case and the receiver settling time is 3 s. The channel filters will be set to have a lower cut-off of 1 MHz. For a timing diagram, please see the receiver parameters section.
streams. In this case, integrated FIR-DACS provide additional filtering. The data streams are sampled with the reference clock. For timing specifications, please see the transmitter parameters section. The wide band IQ upconverter includes spectral shaping reconstruction filters (4th order low-pass Butterworth with 9.75 MHz 3 dB upper cut-off frequency). At +8 dBm maximum transmitter output level the out-of-band (FCC forbidden band) spurious signal power is less than -77 dBc (integrated over 1 MHz with a 100 kHz resolution bandwidth) for the 11 Msymbols/sec CCK modulation (footnote 1). This implies that the spectral regrowth is dominated by any external PA that may be used to boost the transmission power level. In analog mode, it is assumed that the input baseband IQ signals as delivered from the Baseband IC are pulse shaped. By using the on-chip calibration loop, the transmitter Carrier Leakage can be reduced to levels far less than required by the standard. An RF power meter detects the LO level, converts it into a digital signal and a state machine determines the compensation values which are fed through a DAC directly to the IQ inputs. This mode is activated by setting the IC into the DCALIB mode by means of 3-wire bus programming. This calibration is designed to compensate for any DC offsets delivered by the ADCs on the Baseband IC. The DCALIB cannot be used when the IC is using the digital-input Tx mode. The IQ gain and phase imbalance, reconstruction filter roll-off and in-channel noise produce a modulation EVM of less than 12% for 11 Msymbols/sec QPSK. The transmitter has two switched outputs, one with -1.5 dBm output power and the other one with +8 dBm output power. The input pin TX_HI is used to select between the two RF output ports. The 8 dBm output port is differential and is designed to work seamlessly (no external filtering required) with the SA2411 power amplifier. Upon entering the Tx mode, the ramping up of the RF Tx signal is delayed by an internal power ramping circuit. The ramping up time is fixed, while the delay prior to ramping up can be programmed by register settings. Note: When switching out of the Transmit mode (either into Receive mode by transition on TXRX pin, or into another mode by 3-wire programming), the reference clock input (pins XTAL_1 and XTAL_2) needs to be active since a digital timer is being used.
6.8 RSSI
The Receive Signal Strength Indicator (RSSI) is implemented as an error signal comparing the signal level at the Rx output to the nominal value of 500 mVpeak,differential. It has a -10 dBc to +10 dBc operational range relative to the nominal signal level. Since the RSSI acts on the modulated RF signal envelope that is extracted from the baseband I and Q signals, it includes DC offsets, and will therefore show transient decaying errors when the AC coupling lower cut-off frequency is changed. The RSSI signal reflects on a logarithmic scale the amplitude of the instantaneous modulated RF signal (envelope). The RSSI signal is filtered by a low-pass filter with 0.5 MHz upper cut-off frequency. The SA2400A receiver is designed to give at least -10 dBc RSSI at maximum gain, when there is no signal present, i.e., with only thermal noise. However, due to process spreads (e.g., gain, noise figure, IQ low-pass filter bandwidth, etc.), the RSSI may show higher than -10 dBc. In case a calibration is required for setting this noise power to -10 dBc, the AGC's maximum gain (GMAX) can be changed in the range of 85 to 54 dB in steps of 1 dB via register settings. The programmed value of maximum gain is never altered by the AGC settling or by forcing the AGC to maximum gain. Only the RXMGC mode can set the AGC gain to values higher than GMAX. The RXMGC mode does not change the value of GMAX.
6.9 Receiver blocking immunity
The receiver is designed to exceed the IEEE802.11 specifications for the blocking and intermodulation. It can accept continuous or randomly pulsed interfering single- or multi-tone signals that are more than 35 dB stronger than the wanted signal, and up to -10 dBm of interference level. The spurious I and Q outputs are maintained to smaller than -20 dBc of the wanted signal level.
6.10 Transmitter and IQ upconverter
The transmitter inputs are designed to be driven from a Baseband IC in one of two modes: a) in analog mode, differential I and Q inputs expect current signals driven by DACs in the Baseband IC; or b) in digital mode, single-ended inputs expect two binary data
6.11 Reference current and voltage outputs
The IC provides a temperature-constant reference current of 1 mA or 300 A (selectable), active in Tx mode, as well as a 2.5 V reference voltage.
1. For a CCK signal, the peak signal power is 21.7 dB lower than the total power integrated over the 22 MHz band. The SA2400A guarantees better than 56 dBc suppression of the second sidelobe (greater than 22 MHz frequency offset). Consequently, the power level in the forbidden bands is at least 77 dBc below the transmitted integrated power.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
7. OPERATING CONDITIONS Table 3. Absolute Maximum Ratings
Symbol Tstg VDD Parameter Storage temperature Supply voltage Voltage applied to inputs Short circuit duration, to GND or VDD Min -55 -0.5 -0.5 - Max +150 +3.85 VDD+0.5 1 Unit C V V second
Table 4. Recommended Operating Conditions
Symbol Tamb VDD Parameter Ambient operating temperature (Note 1) Supply voltage Min -30 2.85 Nom - 3.3 Max +85 3.6 Units C V
NOTE: 1. When the digital input mode is used, the lower limit of the ambient operating temperature is higher than -30 C. Preliminary characterization results suggest a limit of -20 C. This does not apply if the analog input mode is used.
8. OPERATIONAL MODES AND CURRENT CONSUMPTION
(See also Table 18).
Table 5. Operational modes and current consumption
Tamb = 25 C; VCC = 3.3 V. Chip state POWER-UP SLEEP TX HI Main mode (register 0x04) SLEEP SLEEP TX/RX or FASTTXRXMGC TX/RX or FASTTXRXMGC TX/RX or RXMGC or FASTTXRXMGC Other conditions XO on, clock output on XO off TXRX = HIGH; TX_HI = HIGH TXRX = HIGH; TX_HI = LOW TXRX = LOW Note 1. Synthesizer ON. Transmitter ON with 8 dBm driver. Maximum gain. Synthesizer ON. Transmitter ON with -1.5 dBm driver. Maximum gain. Synthesizer ON. Receiver ON. Receiver gain control by: Description Duration (max.) n/a n/a n/a Current (mA) Min 1.8 - 120 Typ 2.2 - 143 Max 2.7 0.05 170
TX LO
n/a
81
95
105
RX
n/a
81
95
105
* * *
TX/RX internal AGC RXMGC 3-wire bus programming FASTTXRXMGC fast 3-wire bus n/a 3 s 27 - 31 n/a 34 -
WAIT FCALIB
WAIT FCALIB
Only Synthesizer and Xtal oscillator ON Calibrates cut-off frequency of Tx and Rx filters internally. Automatic transition to SLEEP mode upon completion. Maintain TX mode for 5 s before calibration. Quiescent IQ input. Analog mode used. Calibration to reduce transmitter carrier leakage. Automatic transition to SLEEP mode upon completion.
DCALIB
DCALIB
20 s
-
n/a
-
VCOCALIB RESET
VCOCALIB RESET
Calibrates internal VCO. Resets IC into power-up state (SLEEP mode and all registers at default values)
2200 s n/a
- -
n/a n/a
- -
NOTE: 1. All digital inputs connected to GND or VDD.
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
8.1 RESET
Shuts down all blocks except the 3-wire digital section, and programs internal registers to known default values that are described in section 13. This ensures that the SA2400A transmitter, receiver, synthesizer and other blocks enter a known state when made active. The SA2400A enters the SLEEP state automatically after the RESET state. Before entering either the TXRX or RXMGC active states, the internal registers can be reprogrammed to change their values from the default values. A power-up of the digital supply also forces the SA2400A to the RESET mode.
initiated by a 0-to-1 change on the AGC_RESET digital input pin. At any time in the RECEIVE mode, the AGC can be forced to the maximum gain setting by giving a 1 s pulse on the AGC_RESET input while the TX/RX input is held at logic 0.
8.6 FASTTXRXMGC
It is similar to the RXMGC mode, except that the manual AGC gain programming can be done faster, as described in Section 14.5.
8.7 FCALIB
This mode needs to be programmed after power ON in order to internally calibrate the cut-off frequency of the on-chip transmit and receive active filters. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 3 s measured from the end of the programming sequence. The result of this calibration can be read out from register word 0x04.
8.2 SLEEP
All blocks (except the xtal osc) are OFF. The xtal osc can be separately shut down. Note that the 3-wire bus will remain operational in all modes as long as the digital supply is ON. The SA2400A retains programmed values of all active modes when it comes out of the sleep mode. This includes the synthesizer operation. Programmed via 3-wire bus.
8.8 DCALIB
If the analog Tx inputs are used, this mode needs to be programmed at least once after power ON in order to reduce the transmitter carrier leakage. This mode should be programmed after being in TX mode for at least 5 s. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 20 s measured from the end of the programming sequence. The result of this calibration can be read out from register 0x07.
8.3 WAIT
The PLL is on. Receiver and the transmitter are both OFF. This mode is useful for a quick turn-around to either TXRX or RXMGC modes. Transition to or from this mode is done via the 3-wire bus.
8.4 RXMGC
Only the PLL and Receiver are operating. The AGC gain is manually set by the value of a register field.
8.5 TXRX
In this mode the logic level on the TX/RX input pin determines the operational mode: 1 = TRANSMIT, 0 = RECEIVE. This way, no 3-wire bus programming is necessary to switch between Tx and Tx, resulting in faster switching. When entering the RECEIVE mode (either via 3-wire programming to TXRX mode with TX/RX pin at logic zero, or by a 1-to-0 transition of TX/RX pin when already in the TXRX mode), the Receiver is set to maximum gain. An AGC cycle is
8.9 VCOCALIB
This mode needs to be programmed at least once after power ON in order to calibrate the internal VCO. Upon completion of the calibration, the IC will automatically switch to Main Mode = SLEEP. This calibration takes a maximum of 2.2 ms from the end of the programming sequence. After this calibration, the synthesizer must be re-programmed by writing the register words 0x00 through 0x03. The result of this calibration can be read out from register 0x08.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
9. SA2400A RECEIVER
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is 11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the Receiver channel center frequency, as the IF output is at 0 Hz.
Table 6. SA2400A Receiver properties
Tamb = 25 C; VCC = 3.3 V; fLO = 2.45 GHz. Specification RF input frequency range S11 (RF input) Conditions Typical Incl balun+matching. 50 unbalanced. Note 3. LNA in high gain (see reg. description 0x06) LNA in low gain RF input to I or Q outputs Including application, AGCTARGET = +5. Note 1. To maintain nominal IQ output levels as defined below ("nominal I and Q output voltage") IQ Output DC error (relative to signal, 5 s after AGC set) AGC settling time (indicated by AGC_SET digital output) -80 dBm < Pinput < -20 dBm, 1 MHz sinewave output. Note 3. Initiated by AGC_RESET input. Constant RF input within this settling time. Begins after TX to RX switching time. Measured from AGC_RESET 0-1 transition. AGC delay registers (0x05) at default or smaller values. Note 2. a) First instance b) 2nd or subsequent instances AGC forced to GMAX by: a) TX to RX mode transition. (measured after 5 s TX-RX settling time). b) Pulse on AGC_RESET pin (measured from end of programming) Note 2. Note 2. RF input between -75 to -20 dBm. AGC_RESET used. AGC delay registers (0x05) at default values. a) Random (varies each AGC cycle) b) Slow (varies with VCC, Temperature). c) Static (fixed, part to part) With constant RF input during this time. Note 3. a) DC offset < 50% of output signal level b) DC offset <10% of output signal level Output signal within 1 dB of final value, frequency error within 25 ppm of final value. Note 3. Less than the piece-wise linear interpolation. Note 3. Pinput = -85 dBm (LNA in high gain mode) -75 dBm -60 dBm (LNA in low gain mode) -45 dBm 2 interfering tones of power Pinterferer each, at 13 and 23 MHz offsets from LO. IP3 to be more than the piece-wise linear interpolation: Pinterferer = -39 dBm Including matching, receiver at minimum gain. -45 dBm wanted signal at 1 MHz offset, +40 dBc jammer at 25 MHz offset. Note 3. 90 -10 -20 - Min 2.4 -10 -7 93 - - - Typ Max 2.5 - - - - - -20 Units GHz dB dB dB dBm dBm dBc
Maximum Rx voltage gain Max RF input level
-
-
- - - -
8 11 0 3
s s s s
AGC Max Gain settling time
- -
AGC Max Gain adjustment range AGC error (I, Q signal levels)
54 to 85, in steps of 1
dB
-3 -1 -1 - - -
- - - - - 3
3 1 1 8 13 3.5
dB dB dB s s s
DC cancellation time (after ( ft AGCRESET)
TX to RX switching time Noise Figure (I l balun+matching) t hi ) (Incl b l
- - - - -5
7.5 7.5 24 24 1
9 9 25 25 -
dB dB dB dB dBm
Input IP3 (50 source resistance)
1 dB compression of wanted signal Desens by jammer
-10 -
0 -
- 1
dBm dB
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Specification LO leakage to antenna Residual sideband Rejection
Conditions All gain modes. Incl balun Measured with single tone at 2 MHz offset from carrier. Includes both IQ gain and phase error. Notes 3, 7. Note 4. Indicative, not tested. Note 4. DC to ripple band width edge. Note 3. Relative to minimum in-band gain > 11 MHz > 22 MHz Cascade of two 1st order high-pass filters. a) NARROW BAND b) INTERMEDIATE BAND c) WIDE BAND Pin to GND, differential. Pin to GND Differential at the load specified. Note 6. Saturated, differential Programmable (see 0x04) Mode 1 Mode 2 1 MHz tone, differential. Maximum gain. Input 1 - 5 MHz signal, 1 V peak differential sinusoidal at output, output spurs measured differential up to 100 MHz. Ratio of rms total spurious distortion to rms fundamental. Receiver in minimum gain. Note 3. Receiver in maximum gain. Note 3. Note 5.
Min - 22
Typ -75 29
Max -57 -
Units dBm dB
Ripple band width of filter 3 dB band width of filter In-band amplitude ripple Out-of-band attenuation
5.6 - - 25 55 - - - 15 - - -
6.3 7 - - - 10 100 1000 - - 0.5 -
7.0 - 0.6 - - - - - - 6 - 1.5 VCC/2+0.25 1.5 - 4
MHz MHz dB peak dB dB kHz kHz kHz k pF V peak V peak V V V peak %
Lower 3 dB cut-off frequency of AC coupling li
Output load resistance Output load capacitance Nominal I & Q output voltage Maximum I & Q output voltage Common mode IQ voltage
VCC/2-0.25 VCC/2 1.0 1.25 1 - - 2
1 dB compression level at output Total Harmonic Distortion (measured at max and min gains)
- - - 1.25
5 4 0.1 1.55
10 - - 1.95
% deg dB V
Phase Imbalance I, /I to Q, /Q amplitude imbalance RSSI voltage in settled state (internal AGC)
Signal tone input at 2 MHz offset from carrier. Indicative, not tested. ratio of signal at I pin to /I pin; Same for Q and /Q pins. Corresponds to I, Q output signal levels when AGC_RESET is used, with RF input between -10 and -80 dBm. 1 MHz tone, 0.5 V peak differential. ACGTARGET = 0 1 dB change in input power compared to settled state Signal power = -10 dBc Signal power = +10 dBc -10 dBc < signal power < +10 dBc
RSSI voltage difference RSSI minimum voltage RSSI maximum output voltage RSSI error
- - - -
64.5 0.9 2.2 1
- - - -
mV V V dB
NOTES: 1. Corresponds to -15 dBm input level at IC input, assuming typical 5 dB loss from the antenna to the IC input. The AGCTARGET register should be set to "+5" which causes the AGC to settle to an output amplitude greater than the specified nominal value. A resistive divider network at the output can be used to adjust the actual IQ output levels to the BB ADC range. 2. Guaranteed by design. 3. Verified by bench characterization and found to have sufficient margin for production. 4. At power-up time, the filter bandwidth is undefined. It needs to be calibrated with the internal tuner (FCALIB mode). 5. For unsymmetrical loading, attach the same load impedance to the unused pin; condition: for 80% of nominal output voltage swing. 6. Nominal I/Q output levels are understood as the levels the SA2400A will settle to after an AGCRESET action is performed with an RF input signal modulated by a Barker sequence, and with AGCTARGET = 0. 7. RSB = 20*log(sqrt([1+K2 + 2Kcos]/[1+K2 - 2Kcos])), where K = linear gain imbalance, and = phase imbalance.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
9.1 AGC handshake and timing
Th,agcreset Tdsettle Tr,agcreset
TXRX AGCRESET AGCSET Trestart
Treset Tdrxon
Rx TURN-ON
REGULAR SETTLING
SET MAXGAIN
REGULAR SETTLING
SR02417
Figure 3. AGC handshake and timing.
Table 7. AGC timing
Symbol VIH VIL Tr,agcreset Th,agcreset ,g Trestart Tdrxon Treset Tdsettle Parameter HIGH-level logic input voltage LOW-level logic input voltage Input rise time Input hold time Time between AGC cycles (Note 1) Settling time after switching to Rx Clearing time after AGCRESET AGC settling time To execute AGC settling To set AGC to max. Gain AGCSET timing - - - - - - 5 180 11 s ns s Condition Min 0.5xVDD -0.3 - 5 - 1 Typ - - 10 8 0.5 - Max VDD+0.3 0.2xVDD 40 - 1 - Units V V ns s s s AGC logic level requirements
AGCRESET timing
NOTES: 1. In certain time interval further AGCRESET rising edges will not be detected. This applies for 4.3 s < Trestart < 4.8 s.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
10. SA2400A TRANSMITTER
The IQ baseband input signal used is 11 Msymbols/sec QPSK with pulse shaping and 44 MHz D/A sampling rate. The source EVM is less than 3%. The LO frequency is the same as the Transmitter channel center frequency, as the transmit IF input is at 0 Hz.
Table 8. SA2400A Transmitter properties
Tamb = 25 C; VCC = 3.3 V. Specification RF output frequency RF output power incl balun, for a CCK modulated signal Gain step size # gain steps Spectral Mask (Output1) Note 1. N 1 Spectral Mask (Output2) Note 1. Power ramping up time Power ramping up delay (Note 3) Power ramping down Conditions Typical Output1, maximum Output2, maximum Output1 and Output2 Output1 and Output2 -11 to + 11 MHz, 100 kHz band -22 to -11 and 11 to 22 MHz, 100 kHz band < -22, > 22 MHz, 100 kHz band -11 to + 11 MHz, 100 kHz band -22 to -11 and 11 to 22 MHz, 100 kHz band < -22, > 22 MHz, 100 kHz band 10% to 90% ramp up. Note 2. From programming to TRANSMIT mode (TXRX mode, or 0-to-1 change of TX/RX pin). Note 2. Note 2. a) 90% to 10% ramp down b) 10% to carrier leakage level Analog input mode selected. No signal input, only quiescent current. a) Uncalibrated b) Calibrated Digital input mode selected. Carrier Leakage Adjustment Residual Sideband Rejection Error Vector Magnitude RX to TX switching time Adjustment range of input current offset Includes both IQ phase and gain imbalance 11 Msymbols/s QPSK. Both RF outputs. Measured with maximum gain. Note 2. Note 2. a) Output power within 1 dB of final value. Includes 2.5 s for power-up delay and ramping. b) Frequency step settles to within 25 ppm of final value Upper 3 dB cut off frequency, after calibration. Note 2. 1-6 MHz common mode signal at -30 dBc relative to IQ differential signal. Measured at upconverted transmitter output. Note 2. 22-100 MHz common mode signal at -10 dBc relative to IQ differential signal. Measured at upconverted transmitter output relative to in-band 1 MHz tone. Note 2. Into each arm of differential inputs that sink current to ground. Analog input selected. Note 4. Into each arm of differential inputs that sink current to ground. Analog input selected. With 300 A quiescent current into each arm of differential inputs. Analog input selected. Analog input selected. Digital input selected Logic LOW Logic HIGH Min 2.4 4.5 -5 - - - - - - - - - - Typ - 8.0 -1.5 1 15 - -40 -60 - - - 0.5 2 Max 2.5 - - - - 0 -36 -56 0 -30 -50 - - dBc dBc dBc dBc dBc dBc s s Units GHz dBm dBm dB
- - - - - -10 22 -
0.5 0.5 - -40 -40 - - 12
- - -25 -30 -28 +10 - 14
s s dBc dBc dBc A dB %
Carrier Leakage
- - 9.25 30 40
3 3 9.75 - -
3.5 3.5 10.25 - -
s s MHz dB dB
IQ filter bandwidth In-band IQ Common Mode Rejection Ratio Out-of-band IQ Common Mode Rejection Ratio IQ input signal current range IQ input quiescent current Resulting I/Q bias voltage IQ AC input impedance IQ input voltage
50 - 0.6 - - 0.8VDD
- 300 0.7 320 - -
550 - 0.8 - 0.2VDD -
A A V V V
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Specification IQ input timing
Conditions Digital input selected, sampling on falling edge, li REF CLK OUT relative to REF_CLK_OUT Set-up time Hold time
Min - -
Typ 4 4
Max - -
Units ns ns
NOTES: 1. The 44 MHz common mode digital ground bounce on the I and Q inputs is assumed to be less than -30 dBc relative to signal level. 2. Verified by bench characterization and found to have sufficient margin for production. 3. The power ramping-up delay can be programmed to 2, 3, 4, 5 s. See the 3-wire bus control register map. The default is 2 s. 4. The differential input signal current is the difference between the I and /I (Q and /Q) instantaneous currents. The peak differential current is therefore (Imax-Imin)/2 = 500 A.
11. VCO AND SYNTHESIZER
Table 9 lists the synthesizer specifications. The synthesizer has the same specification as the SA8027 fractional PLL main loop without the PHI speed-up mode. The phase comparator frequency used is typically 4 MHz (in fractional mode). The charge pump current is internally programmed using the 3-wire bus (Synthesizer Register C). The recommended charge pump current is 480 A. An external reference input of 44 MHz or 22 MHz is supported.
Table 9. Synthesizer and VCO Specifications
Tamb = 25 C; VCC = +3 V LIMITS PARAMETER VCO VCO output frequency range VCO gain (KVCO) Open Loop VCO Phase Noise External VCO input levels Main divider N divider range Reference divider Fixed reference input (XTAL_1 and XTAL_2) f frequency R divider range (non-fractional) Reference input level Input parallel resistance (XTAL_1, XTAL_2) Input parallel capacitance (XTAL_1, XTAL_2) Phase detector Phase detector frequency Charge pump Charge pump current accuracy Charge pump compliance voltage Output current variation vs. Vcp (Note 2) Charge pump sink to source current Matching Charge pump "off" current leakage Vcp in compliance range Vcp = 0.5 VCC Vcp = 0.5 VCC Vcp = 0.5 VCC -20 0.6 -5 -10 -5 - - - - 1 +20 VDD - 0.7 +5 +10 5 % V % % nA - - 4.0 MHz SM = `000' XTAL_1 input f = 44 MHz; indicative, not tested f = 44 MHz; indicative, not tested - - 4 350 10 - 22 44 - - - - - - 1023 1300 - 1.5 mVpp k pF MHz MHz 512 - 65535 Vtune = 1.2 V Note 1. 1/f2 roll off region; 0.5 MHz offset Differential; when device configured for external VCO 2.4 70 - -10 - 85 -113 - 2.5 100 -107 0 GHz MHz/V dBc/Hz dBm TEST CONDITIONS Min Typ Max UNITS
NOTES: 1. This is measured at the Output1 RF port with the SA2400A in transmit mode, with static DC offset signals to the transmitter I and Q inputs. The phase detector and divide-by-N phase noise is such that when configured as a phase locked loop with a 30 kHz loop band width, the phase noise at frequencies between 1 kHz and 30 kHz will be no worse than -80 dBc/Hz. The total closed loop spur power within a 22 MHz band around the carrier is less than -30 dBc. (I 2 * I 1) 2. The relative output current variation is defined as: DI ZOUT + 2 I OUT I2 ) I1 with I1 @ V1 = 0.6 V, I2 @ V2 = VCC - 0.7 V (see Figure 4).
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
CURRENT
IZOUT
I2
I1
VOLTAGE V1 V2
VPH
I2
I1
SR00602
Figure 4.
12. FUNCTIONAL DESCRIPTION 12.1 Main Fractional-N divider
The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 512 to 65535. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented by the value of NF. The accumulator works with modulo Q set by FM (Synthesizer Register A). When the accumulator overflows, the overall division ratio N will be increased by 1 to N + 1, the average division ratio over Q main divider cycles (either 5 or 8) will be NF Nfrac + N ) Q
The output of the main divider will be modulated with a fractional phase ripple. The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance.
12.2 Reference divider
The reference divider consists of a divider with programmable values between 4 and 1023 followed by a 3-bit binary counter. The 3-bit SM register (see Figure 5) determines which of the five output pulses are selected as the main phase detector input.
SM="000" SM="001" SM="010" SM="011" SM="100" TO MAIN PHASE DETECTOR
REFERENCE INPUT
DIVIDE BY R
/2
/2
/2
/2
SR02354
Figure 5. Reference Divider
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
12.3 Phase detector (see Figure 6)
The reference and main divider outputs are connected to a phase/frequency detector that controls the charge pump. The pump current is set by the control bit CP (Synthesizer Register C). The
dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps ON for a minimum time () at every cycle (backlash time) providing improved linearity.
VCC P-TYPE CHARGE PUMP
1 D fREF REF DIVIDER R CLK R Q
P
1 fRF MAIN DIVIDER M D CLK Q N R
IPH
N-TYPE CHARGE PUMP
GND
fREF
R
M
P
N
IPH
SR02355
Figure 6. Phase Detector Structure with Timing
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
12.4 Main output charge pumps and fractional compensation currents (see Figure 7)
The main charge pumps on pin CP are driven by the main phase detector and the charge pump current value is determined by bit CP (Synthesizer Register C). The fractional compensation is derived from the contents of the fractional accumulator FRD and by the program value of the FDAC. The timing for the fractional compensation is derived from the main divider. The charge pumps will enter speed-up mode after sending a Synthesizer Register A word and stays active until a different word is sent.
accumulator value and is adjusted by FDAC values (bits FC7-0 in Synthesizer B). The fractional compensation current is derived from the main charge pump in that it follows all the current scaling through programming or speed-up operation. For a given charge pump, ICOMP = (IPUMP / 128) * (FDAC / 5*128) * FRD FRD is the fractional accumulator value. The target values for FDAC are: 128 for FM = 1 (modulo 5) and 80 for FM = 0 (modulo 8).
12.6 Lock Detect
The output LOCK maintains a logic `1' when main phase detector indicates a lock condition. The lock condition is defined as a phase difference of less than 1 period of the frequency at the input XTAL_1, XTAL_2. Out of lock (logic `0') is indicated when the synthesizer is powered down.
12.5 Principle of fractional compensation
The fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. If ICOMP is the compensation current and IPUMP is the pump current: IPUMP_TOTAL = IPUMP + ICOMP. The compensation is done by sourcing a small current, ICOMP, see Figure 8, that is proportional to the fractional error phase. For proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. The width of the fractional compensation pulse is fixed to 128 VCO cycles, the amplitude is proportional to the fractional
12.7 Power-down mode
The power-on signal is defined by the bit ON in Synthesizer Register B. If ON = `1', the synthesizer section is powered on/off as defined by the chip mode (register 0x04). If ON = `0', it is defined as inverted to the chip mode. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
REF. DIVIDER OUTPUT R MAIN DIVIDER OUTPUT M N N N+1 N N+1
DETECTOR OUTPUT
2
4
1
3
0
ACCUMULATOR FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION OUTPUT ON PUMP PULSE LEVEL MODULATION
mA
A
SR01416
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 7. Waveforms for NF = 2 Modulo 5 fraction = 2/5
fRF
MAIN DIVIDER
FRACTIONAL ACCUMULATOR ICOMP IPUMP
fREF
LOOP FILTER & VCO
SR01800
Figure 8. Current Injection Concept
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
13. SA2400A OTHER FUNCTIONALITY
Table 10 specifies functionality not described elsewhere in this document.
Table 10. SA2400A Other Functionality
Tamb = 25 C; VCC = 3.3 V LIMITS PARAMETER Reference voltage output, pin V_2P5 Reference current output, pin IDCOUT TEST CONDITIONS ILOAD < 2 mA, CLOAD < 10 pF; switched on via register 0x04 bit 14 = `1' Register 0x04 bit 12 = `1'; "sink current" measured from supply to IC pin Register 0x04 bit 13 = `1'; "source current" measured from IC pin to ground Min 2.25 0.25 0.85 Typ 2.5 0.3 1.0 Max 2.75 0.35 1.15 UNITS V mA mA
14. 3-WIRE BUS/LOGIC CONTROL
A simple 3-line bi-directional serial bus is used to program the circuit. The 3 lines are SDATA, SCLK and SEN. The SDATA line is bi-directional while the SCLK and SEN signals are always supplied externally:
* The pin SEN is an "enable" signal. It is level sensitive: If SEN is of
LOW value, the 3-wire bus interface on the SA2400A is enabled. This means that each rising edge on the SCLK pin (see below) will be taken as a shift cycle, and address/data bits are expected on SDATA (see below). If SEN is HIGH, the 3-wire bus interface is disabled. No register settings will change regardless of activity on SCLK and SDATA.
The 3-wire bus interface contains an internal counter (state machine) which determines beginning and end of address and data word, the "write" pulse to the internal registers, and the direction of the bi-directional SDATA pin. Consequently, with the 32nd rising SCLK edge of a WRITE cycle, the current data word is stored in the internal register of the programmed address. Following SCLK edges will be taken as the beginning of the following cycle. No programming on SEN is needed to separate cycles. If the SEN signal is switched to HIGH (i.e., DISABLE) at any time, the current cycle will be disregarded. Any bits that have been shifted in so far via SDATA will be disregarded. The internal counter is reset to zero.
* The pin SCLK is the "shift clock" input. If the 3-wire bus is
enabled, address or data bits will be clocked in from the SDATA pin with rising edges of SCLK. In output mode, SDATA bits are set on the falling edge of SCLK in order to be sampled on the rising edge by the controller.
14.1 Description of WRITE cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is enabled. 2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first. The bit values on SDATA are taken over with rising edges on SCLK. 3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising edge of SCLK. `1' = WRITE, `0' = READ. 4. (SCLK edges 9 through 32) 24 data bits are clocked in, LSB first, with rising edges of SCLK. With the 32nd rising edge of SCLK, the whole data word is stored in the internal register according to the selected address.
* The pin SDATA is the bi-directional "data" pin. It is internally
configured as "input" or "output" depending on the operation (WRITE or READ). Each operation consists of 32 bits. Out of these, the first 7 bits form an address word, followed by a READ/WRITE indicator bit. The following 24 bits are the data word corresponding to the chosen address.
Tcyc 1 SCLK 2 3 4 5 6 7 8 9
tr 10
tf 11 32 1
SEN
SDATA
A0 Ton
A1
A2
A3 Tsetup Thold
A4
A5
A6
R/W
D0
D1
D2
D23
SR02288
Figure 9. WRITE cycle timing diagram of the 3-wire bus
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
14.2 Description of READ cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is enabled. 2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first. The bit values on SDATA are taken over with rising edges on SCLK.
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising edge of SCLK. `1' = WRITE, `0' = READ. 4. (SCLK edges 9 through 32) 24 data bits are clocked out, LSB first. The bits will be available on the SDATA pin with the falling edges of SCLK (so bits can be accepted by the baseband IC with the following rising edge).
Tcyc 1 SCLK 2 3 4 5 6 7 8 9
tr 10
tf 11 32 1
SEN
SDATA
A0 Ton
A1
A2
A3 Tsetup Thold
A4
A5
A6
R/W
D0 Tdout
D1
D2
D23
SR02289
Figure 10. READ cycle timing diagram of the 3-wire bus The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new data even during power-down. The data remains latched during power-down (sleep mode).
14.3 3-wire bus/logic control AC characteristics Table 11. 3-wire bus/logic control AC characteristics
LIMITS SYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNITS
Serial Bus Logic Level Requirements VIH VIL tr tf Tcyc Ton Tsetup Thold Tdout HIGH logic input voltage LOW logic input voltage 0.5xVDD -0.3 - - VDD + 0.3 0.2xVDD 40 40 - V V
Serial Programming Clock, SCLK Input rise time Input fall time Clock period - - 22 10 10 100 ns ns ns
Enable Programming, SEN Delay to rising clock edge 10 - - ns
Data Programming, SDATA Input data to clock set-up time Input data to clock hold time Output data to clock delay time (falling edge) - - - 10 10 - - - - - - 10 ns ns ns
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
14.4 3-wire bus control register map
14.4.1 Data Format
Table 12. Format of programmed data
LAST IN (MSB) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 FIRST IN (LSB) 6 5 4 3 2 1 0
Table 13. Overview
Address 00 01 02 03 04 05 06 07 08 Description Synthesizer: Main divider settings WRITE ONLY Synthesizer: Reference divider and fractional compensation WRITE ONLY Synthesizer: charge pump current and additional division WRITE ONLY Synthesizer: test modes WRITE ONLY Main operation modes, filter tuner, other controls Rx AGC adjustment settings Manual receiver control settings Transmitter settings VCO settings (only bits 0 through 9)
NOTES: 1. The synthesizer registers (addresses 00 to 03) cannot be read. 2. After programming register 0x01 it is necessary to also program register 0x00 to load the content of FC[7:0] into the internal working register. 3. After programming register 0x00 it is necessary to program some other register (e.g., 0x04) to avoid keeping the charge pump current setting in php-speedup mode. 4. After running the VCOCALIB mode, it is necessary to re-program registers 0x00 through 0x03.
Table 14. Address 00: Synthesizer Register A
Note: Bits 22, 23 not used. Main divider register Bit Name Default Bit FM NF[2:0] N[15:0] 21 FM 0 1 20 19 NF[2:0] 0 0 0 0 0 0 0 0 1 18 17 16 15 14 13 12 11 10 0 9 0 8 1 7 1 6 0 5 0 4 1 3 1 2 1 1 0 0 0 N[15:0] unused
Description Fractional modulus select. 0->/8; 1->/5; default: 0 Fractional increment value (0 to 7); default: 4 Main divider division ration (512 to 65535); default: 615
Table 15. Address 01: Synthesizer Register B
Note: Bits 22, 23 not used. Bit Name Default Bit R[9:0] L[1:0] 0 0 0 0 21 20 19 18 17 0 16 0 15 1 14 0 13 1 12 1 11 L 1 0 10 9 ON 1 1 0 1 0 8 7 6 5 4 1 3 0 2 0 1 0 0 0 R[9:0] FC[7:0]
Description Reference divider ratio (4 to 1023); default: 11 lock detect mode 00-> inactive 01-> inactive 10->lock detect normal mode 11->inactive Power On/Off 1: as defined by chip mode (register 0x04) 0: inverted chip mode control Fractional compensation charge pump current DAC (0 to 255); default: 80
ON FC[7:0]
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 16. Address 02: Synthesizer Register C
Note: Bits 22, 23 not used. Bit Name Default Bit CP[1:0] SM[2:0] 0 0 0 0 0 0 21 20 19 18 17 16 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 0 5 0 4 SM[2:0] 0 0 3 2 `0' 0 1 0 0 0 unused CP[1:0] unused
Description Charge pump current setting Comparison divider select Adds an extra divider at the end of the reference divider: extra division ratio = 2^SM (SM = 0 to 4) php 480 A 160 A 480 A 160 A php-speedup 2.4 mA 800 A 2.4 mA 800 A
CP[1:0] 00 01 10 11
php-speedup is activated when the speed-up bit is 1 (Tspu in synthesizer register D). php-speedup is also entered after sending a synthesizer register A word and stays active until a different word is sent. To prevent frequency deviations when leaving the speedup mode when programming new words, it is recommended to keep the speedup mode always disabled by setting the Tphpsu (0x03, bit 16) to `1'. NOTE: The only recommended charge pump current setting mode is CP[1:0] = 10, php-speedup not activated.
Table 17. Address 03: Synthesizer Register D
Note: Bits 22, 23 not used. Bit Name Default Bit Tphpsu Tspu 0 0 21 20 19 `00000' 0 0 0 18 17 16 Tphpsu 0 15 Tspu 0 0 0 0 0 14 13 12 11 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 unused 0 0 0 `000000000000'
Description 1 -> disable PHP speedup pump, overrides function of Tspu 1 -> speedup ON 0 -> speedup OFF
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 18. Address 04: Main chip operation modes, filter tuner, other controls
Bit Name Default Bit # 0-3 0 Name Chip mode 23 22 0 21 0 20 0 19 adc 0 18 fterr 0 0 17 16 Filttune 1 1 15 14 v2p5 0 13 I1m 0 12 I0p3 1 11 n.u. 0 10 in22 0 9 clk 1 8 xo 1 7 digin 0 6 rxlv 0 5 veo 0 4 vei 0 0 3 2 0 1 0 0 0 `0000' Chip mode
Description Main mode of operation. Coding according to following table: Bit3 0 0 0 0 0 0 0 0 1 Bit2 0 0 0 0 1 1 1 1 0 Bit1 0 0 1 1 0 0 1 1 0 Bit0 0 1 0 1 0 1 0 1 0 Mode SLEEP TX/RX WAIT RXMGC FCALIB DCALIB FASTTXRXMGC RESET VCOCALIB
Notes on modes: * All calibration modes (*CALIB) require the crystal oscillator to be ON (bit XO = 1). * DCALIB (Tx LO leakage calibration) requires being in Tx mode for 5 s before calibration. 4 5 6 7 8 9 10 11 12 13 14 15-17 vei veo rxlv digin xo clk in22 Not used I0p3 I1m v2p5 filttune External reference current (pad idcout): 0.3 mA to ground External reference current (pad idcout): 1.0 mA from supply External reference voltage (pad v2p5) ON Rx and Tx filter tuning bits: Write: (with test mode only), these bits set tuning value Read: (in normal mode) tuner setting can be read out here Filter tuner error (read only): result is 1 when tuner exceeded range `1': in Rx mode, the RSSI-ADC is always on. `0': the RSSI-ADC is only on during AGC operation. Use external vco input (vcoextin) Make internal vco available at vco pads (vcoextout) Rx output common mode voltage: 0-VDD/2, 1-1.25 V Use digital Tx inputs (FIRDAC) Xtal oscillator ON Reference clock output ON Xtal input frequency: 0-44 MHz, 1-22 MHz
18 19
fterr adc
Table 19. Address 05: AGC adjustment settings
Bit Name Default Bit # 0-4 5-9 10-14 23 (0) Name AGC_rxondel/s1 AGC_lnadel/s2 AGC_bbdel/ADCval 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rx AGC target val(000) Rx AGC Gmax 79 dB - 11001 Description Write: Programmable delay for AGC algorithm: Rx turn-on to AGCSET. In units of 182 ns (5.5 MHz) Read: 1st sample of RSSI in AGC cycle Write: Programmable delay for AGC algorithm: Settling time after LNA gain switching. In units of 182 ns (5.5 MHz) Read: 2nd sample of RSSI in AGC cycle Write: Programmable delay for AGC algorithm: Settling time after baseband gain switching. In units of 182 ns (5.5 MHz) Read: Output of RSSI/Tx-peak detector ADC in 5-bit Gray code Rx AGC gain limit (54 dB + programmed value) (valid: 54 through 85) Adjustment value to AGC settling target, range -7 dB ... 7 dB (sign plus three bits) 22 AGC_bbdel/ADCval 7(1.3 s) - 00111 AGC_lnadel/sample2 15(2.7 s) - 01111 AGC_rxondel/sample1 27(4.9 s) - 11011
15-19 20-23
AGC Gmax AGC target
2002 Nov 04
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 20. Address 06: Manual receiver control settings
Bit Name Default Bit # 0-9 23 ahsn 0 Name receiver gain 22 osQ 0 (0) 21 20 19 18 17 osI 0 (0) 16 15 14 val (000) 13 12 ten 1 11 0 10 0 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 rxosQval val (000) rxosIval Corner f Receiver gain
Description Write: In RXMGC mode, this sets the receiver gain. Read: In other modes, the AGC controlled gain is available for readout here. Bit positions: 0-plus1dB; 1-vga2dB; 2-vga4dB; 3-vga8dB; 4-vga16dB; 5-vga10dB; 6-filter6dB2; 7-filter10dB; 8-filter6dB1; 9-lna16dB DC offset cancellation cornerpoint select. Write: In RXMGC mode, this sets the cornerpoint. Read: In other modes, the cornerpoint as controlled by the AGC is available for readout here. Code: 00-10 kHz, 01-100 kHz, 10-1 MHz, 11-10 MHz Use 10 MHz offset cancellation cornerpoint for brief period after each gain change Receiver output driver manual offset adjustment. Code: {rxosXon,rxosXval} = `0xxxx' offset = 0; {rxosXon,rxosXval} = `10000' offset = 8 mV; {rxosXon,rxosXval} = `11000' offset = -8 mV; {rxosXon,rxosXval} = `10001' offset = 16 mV etc. Rx offset correction, I channel, value (sign plus three bits) Rx offset correction, I channel, ON Rx offset correction, Q channel, value (sign plus three bits) Rx offset correction, Q channel, ON AGC with high Signal-to-Noise (switch LNA at step 52 instead of step 60). Recommended to set to `1'.
10-11
corner freq.
12 13-22
ten Rx offset I,Q
13-16 17 18-21 22 23
rxosIval rxosIon rxosQval rxosQon ahsn
Table 21. Address 07: Transmitter settings
Bit Name Default Bit # 0-3 4-7 8-9 10-19 0 Name Tx gain low Tx gain hi txramp Tx offset I, Q 23 22 0 21 0 20 0 19 osQ 0 (0) 18 17 16 val (000) 15 14 osI 0 (0) 13 12 11 val (000) 10 9 0 8 0 7 6 5 4 3 2 1 0 `0000' TxosQval txosIval txramp Tx gain hi 0 dB (0000) Tx gain low 15 dB (1111)
Description Transmitter gain settings for TXLO output Transmitter gain settings for TXHI output Tx ramp-up delay programming: 00-1 s, 01-2 s, 10-3 s, 11-4 s. Ramp-up time always 1 s. Tx carrier leakage calibration: Write: with test mode, these bits set the offset. Read: in normal mode, automatically controlled settings can be read out here (sign plus three bits). Code: {txosXon,txosXval} = `0xxxx' offset = 0; {txosXon,txosXval} = `10000' offset = 2.5 A; {txosXon,txosXval} = `11000' offset = -2.5 A; {txosXon,txosXval} = `10001' offset = 5.0 A etc. Tx offset correction, I channel, value (sign plus three bits) Tx offset correction, I channel ON Tx offset correction, Q channel, value (sign plus three bits) Tx offset correction, Q channel ON
10-13 14 15-18 19
txosIval txosIon txsoQval txosQon
Table 22. Address 08: VCO settings
Bit name default Bit # 0-3 x Name vcoband x x x 23 22 21 20 19 x 18 x 17 x 16 x 15 x 14 x 13 x 12 x 11 x 10 x 9 0 8 not used 0 0 7 6 `0' 0 5 `0' 0 4 vcerr 0 0 3 2 0 1 0 0 0 these bits do not exist on IC vcoband
Description VCO band. Write: with test mode, these bits set the VCO band. Read: in normal mode, the result ot the calibration (VCOCAL) can be read out here (0000 = highest frequencies). VCO calibration error flag (no band with low enough frequency could be found).
4
vcerr
2002 Nov 04
23
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
14.4.2 Programming Example Program synthesizer for 2.412 GHz band reference division ratio R = 11
14.5 Fast serial interface for Receiver-AGC programming
When the chip is in mode "FASTTXRXMGC" the internal AGC block is disabled. Instead, the 10 bits controlling the receiver gain and the two bits controlling the DC offset cancellation corner frequency can be programmed directly via a dedicated second serial interface. This interface is active when in FASTTXRXMGC mode and when SEN=HIGH. (SEN acts as a switch between the regular serial interface and the dedicated bus). 14.5.1 Description of "fast programming" cycle 1. Set the chip to FASTTXRXMGC mode by programming register 4 with the correct value. 2. Set the SEN pin to HIGH. 3. With each rising edge on pin SCLK, a new data bit is expected at pin AGCRESET. No address is needed. The sequence of the bits is the same as described for register 6, bits 0-11. The programming order is LSB first. 4. With the 12th rising edge on SCLK, an internal counter will automatically parallel-load the shifted-in data bits into an internal register. The bits will immediately effect the receiver settings. 5. The regular 3-wire bus is still accessible and can be programmed when SEN is LOW. Clock activity on SCLK will not affect receiver gain settings when SEN is LOW.
* Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz * Target frequency is 2412 MHz, fcomp = 4 MHz main divider ratio
N = 603 (no fractional N) - write this word to register 00: 00 0 000 0000001001011011 00 (note two leading zeros - unused bits 22, 23) - write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx (x = no significance) Program synthesizer for 2.462 GHz band reference division ratio R = 11
* Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz * Target frequency is 2462 MHz, fcomp = 4 MHz main divider ratio
N = 615.5 (fractional 4/8) - write this word to register 00: 00 0 100 0000001001100111 00 - write this word to register 01: 00 0000001011 00 1 0 01010000 Fractional compensation setting should be set in the application (depends on the loop parameters) with the help of the SA8027 application note. The nominal value is FC = 640 / FM (FM = modulus, see address 00).
Tcyc 1 SCLK 2 31 32 1 2 3 4
tr tf 5 11 12 1
SEN
SDATA AGCRESET
A0
A1
D23
D23
XX D0 Ton D1 D2 D3 D4 Tsetup Thold D10 D11
A0 XX
3-WIRE BUS PROGRAMMING
"FAST BUS" PROGRAMMING
SR02311
Figure 11. "Fast programming" cycle timing diagram
14.6 Fast serial interface AC characteristics
SYMBOL PARAMETER TEST CONDITIONS LIMITS Min 0.5xVDD -0.3 - - 22 10 10 10 24 Typ - - 10 10 100 - - - Max VDD + 0.3 0.2xVDD 40 40 - - - - UNITS
Serial Bus Logic Level Requirements VIH VIL tr tf Tcyc Ton Tsetup Thold 2002 Nov 04 HIGH logic input voltage LOW logic input voltage Input rise time Input fall time Clock period Delay to rising clock edge Input data to clock set-up time Input data to clock hold time V V ns ns ns ns ns ns
Serial Programming Clock, SCLK
Enable Programming, SEN Data Programming, AGCRESET
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
15. PERFORMANCE CURVES
3.5 3.0 2.5 TIME (s) 2.0 1.5 1.0 FREQ. (s) 0.5 0 -40 Pout (s) -15 10 35 60 85 27.5 -40 -15 10 35 60 85 SIDE BAND REJECTION (dB) 30.5
30.0
29.5
29.0
28.5
28.0
TEMPERATURE (C)
TEMPERATURE (C)
SR02418
SR02420
Figure 12. TX to RX switching time versus temperature (VDD = 3.3 V)
4.0 3.5 3.0 TIME (s) 2.5 2.0 1.5 1.0 FREQ. (s) 0.5 0 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE, VDD (V) Pout (s) SIDE BAND REJECTION (dB)
Figure 15. RX residual sideband suppression versus temperature (VDD = 3.3 V)
32.5 32.0 31.5 31.0 30.5 30.0 29.5 29.0 28.5 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE, VDD (V)
SR02419
SR02821
Figure 13. TX to RX switching time versus supply voltage (Tamb = 25 C)
30
Figure 16. RX residual sideband suppression versus supply voltage (Tamb = 25 C)
0
25 NOISE FIGURE (dB)
-10
2.7V 15 2.85V 10 3V 3.3V 5 3.6V 0 -85
POWER (dBm) -45
20
-20
-30
-40
-50
-60 -75 -65 INPUT POWER (dBm) -55 9.50E+07 9.70E+07 9.90E+07 1.01E+08 1.03E+08 1.05E+08 FREQUENCY (Hz)
SR02427
SR02822
Figure 14. Noise Figure versus input power
Figure 17. Spectrum of RX sideband rejection at 4 MHz offset
2002 Nov 04
25
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
12.2 ERROR VECTOR MAGNITUDE (%) 12.0 11.8 11.6 11.4 11.2 11.0 10.8 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE, VDD (V)
SR02460
SR02824
Figure 18. TX ramp-up (1 s/div).
Figure 21. Transmitter error vector magnitude (EVM) versus supply voltage (Tamb = 25 C).
3.5
25 LOW HIGH 20 TIME (s)
3.0 2.5 2.0 1.5 1.0 FREQ. (s) 0.5 Pout (s) -15 10 35 60 85
NF (dB)
15
10
5 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 Pin (dBm)
0 -40
TEMPERATURE (C)
SR02461
SR02425
Figure 19. Noise Figure vs. input power for two LNA switching modes.
12 ERROR VECTOR MAGNITUDE (%)
Figure 22. RX to TX switching time versus temperature (VDD = 3.3 V).
3.5 3.0 2.5 TIME (s) 2.0 1.5 1.0
10
8
6
4 FREQ. (s) 0.5 0 2.7 Pout (s) 3.0 3.3 3.6
2
0 -40
-15
10
35
60
85
TEMPERATURE (C)
SUPPLY VOLTAGE, VDD (V)
SR02423
SR02426
Figure 20. Transmitter error vector magnitude (EVM) versus temperature (VDD = 3.3 V).
Figure 23. RX to TX switching time versus supply voltage (Tamb = 25 C).
2002 Nov 04
26
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
SR02459
Figure 24. TX constellation and EVM.
2002 Nov 04
27
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
6.00 5.00 4.00 MEAN (A) 3.00 2.00 1.00 0.00 -1.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.30 V 2.85 V 3.00 V 2.70 V
SR02445
Figure 25. Total sleep ICC.
124.00 2.70 V 120.00 MEAN (MHz) 116.00 112.00 108.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.00 V 3.30 V 2.85 V
SR02446
Figure 26. VCO 0011 bandwidth.
2448.00 2.70 V 2420.00 MEAN (MHz) 2392.00 3.00 V 3.30 V -30 0 25 TEMPERATURE (C) 70 85 3.60 V 2.85 V
2364.00
SR02447
Figure 27. VCO 0111 f1.
105.00 2.70 V 96.00 MEAN (mA) 87.00 2.85 V 3.00 V 3.30 V -30 0 25 TEMPERATURE (C) 70 85 3.60 V
78.00
SR02448
Figure 28. Total TX LOW ICC.
2002 Nov 04
28
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
0.00 MEAN (dBm) -5.00 2.70 V 2.85 V 3.00 V -10.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.30 V
SR02449
Figure 29. Output power TX LOW, g = 1111.
160.00 2.70 V 150.00 MEAN (mA) 140.00 130.00 120.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.00 V 3.30 V 2.85 V
SR02450
Figure 30. Total TX HIGH ICC.
10.00 2.70 V MEAN (dBm) 2.85 V 5.00 3.00 V 0.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.30 V
SR02451
Figure 31. Output power TX HIGH, g = 1111.
-108.00 2.70 V -110.00 MEAN (dBc/Hz) -112.00 3.00 V 3.30 V -30 0 25 TEMPERATURE (C) 70 85 3.60 V 2.85 V
-114.00
SR02452
Figure 32. PLL phase noise @ 500 kHz.
2002 Nov 04
29
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
-34.00 2.70 V -41.00 2.85 V MEAN (dBc) -48.00 -55.00 -62.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.00 V 3.30 V
SR02453
Figure 33. TX HIGH spectral mask, adjacent channel.
-30.00 2.70 V -40.00 MEAN (dBc) -50.00 3.00 V 3.30 V -30 0 25 TEMPERATURE (C) 70 85 3.60 V 2.85 V
-60.00
SR02454
Figure 34. TX LOW spectral mask, adjacent channel.
104.00 2.70 V 98.00 2.85 V MEAN (mA) 92.00 86.00 80.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.00 V 3.30 V
SR02455
Figure 35. Total RX ICC.
94.00 92.00 90.00 MEAN (dB) 88.00 3.00 V 86.00 84.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.30 V 2.70 V 2.85 V
SR02456
Figure 36. RXMGC I max gain.
2002 Nov 04
30
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
94.00 92.00 90.00 MEAN (dB) 88.00 3.00 V 86.00 84.00 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.30 V 2.70 V 2.85 V
SR02457
Figure 37. RXMGC Q max gain.
6.85 2.70 V 6.70 MEAN (MHz) 6.55 6.40 6.25 -30 0 25 TEMPERATURE (C) 70 85 3.60 V 3.00 V 3.30 V 2.85 V
SR02458
Figure 38. RX filter ripple bandwidth.
2002 Nov 04
31
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
2002 Nov 04
32
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
REVISION HISTORY
Rev _1 Date 20021104 Description Product data; initial version. Engineering Change Notice 853-2320 28727 (date: 20020809).
2002 Nov 04
33
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 11-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09632
Philips Semiconductors
2002 Nov 04 34

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